A data processing apparatus may be provided with at least one cache, so that the latency associated with retrieving data items from memory can largely be avoided for data items which are frequently accessed, by storing copies of these data items in the cache storage. Moreover, more than one level of cache may be provided, arranged as a cache hierarchy, wherein a smaller faster cache is provided closer to the processing circuitry which requires use of the data item copies, whilst a larger cache is provided further away, but which nonetheless allows faster access to the copies of data items it stores than accessing those original data items in the memory. Typically, these cache levels are referred to as level 1 and level 2 respectively. Furthermore, the usual arrangement is for the level 2 cache to store a subset of the data items available in the memory, whilst the level 1 cache stores a subset of the data items available in the level 2 cache. Nevertheless, instruction cache lines and data cache lines may be handled differently in regard to their storage in the cache hierarchy. For example, separate instruction and data caches may be provided at level 1, whilst a unified cache which stores both instruction lines and data lines may be provided at level 2. Furthermore, when a dedicated level 1 instruction cache is large enough for the instruction code working set of a typical user application to be captured entirely within the level 1 instruction cache, the cache hierarchy may be configured such that instruction cache lines are written directly into the level 1 instruction cache, bypassing the level 2 cache and preserving space therein for other purposes.